1. Technical Field of the Invention
The present invention relates generally to semiconductor packages and, more particularly, to a semiconductor package including supporting stiffening and heat spreading characteristics.
2. Description of Related Art
Reference is made to FIGS. 1-3 which illustrate a sequence of process steps for producing a semiconductor package. FIG. 1 shows an organic substrate printed wire board 10. A semiconductor die 12 is attached to a top surface of the organic substrate printed wire board 10 using an under fill adhesive 14. FIG. 2 shows a stiffener ring 16 that has been attached to the top surface of the organic substrate printed wire board 10. The ring 16 surrounds the die 12 and has an outer perimeter edge coincident with an outer perimeter edge of the organic substrate printed wire board 10. An inner edge of the ring 16 is spaced away from an outer edge of the die 12. The ring 16 is attached to the organic substrate printed wire board 10 top surface using any suitable adhesive material. FIG. 3 shows a heat spreader 18 that has been attached to the top surface of the ring 16. The heat spreader 18 is illustrated to be in the form of a thermally conductive plate. The heat spreader 18 may, as shown, have an outer perimeter edge coincident with the outer perimeter edges of the ring 16 and organic substrate printed wire board 10. The spreader 18 is attached to the ring 16 top surface using any suitable adhesive material. A thermally conductive material 20 (also known in the art as a thermal interface material), which may also comprise an adhesive, is positioned between a top surface of the die 12 and a bottom surface of the heat spreader 18.
Reference is now made to FIG. 4 which illustrates package warpage for the semiconductor package shown in FIG. 3. FIG. 4 illustrates only one-quarter of the package due to symmetry. The warpage level is highest in the region 24 near the location of the die 12 and lowest in the region 26 at a corner of the package furthest away from the die 12. The dotted lines 28 indicate the gradient change in warpage moving away from the center of the package toward the perimeter of the package. FIG. 4 was obtained from finite element modeling, and shows the displacement contour of the package in FIG. 3 when cooling down to room temperature for the under fill curing process.
Reference is now made to FIG. 5 which illustrates maximum stress in the semiconductor die 12 for the semiconductor package shown in FIG. 3. FIG. 5 illustrates the stress contour on the die 12 obtained by finite element modeling. Only one-quarter of the die 12 was modeled due to symmetry. The maximum stress level is highest in the region 32 near the corner of the die 12 and decreases moving away from the region 34. The dotted lines 34 indicate the gradient change in maximum stress level.